Zero-voltage and frequency pattern selection for DC-link loss minimization in PWM-VSI drives

Abstract The modulation of a voltage source inverter output causes losses and harmonic distortions on the load side DC-link capacitor due to discrete switching semiconductors. High-frequent pulses are digitally programmed control determine distortions. This paper presents an optimization in terms pulse- frequency-pattern selection for reducing while keeping minimal. In detail, fact that pulse frequency patterns independent from each other is utilized modified three-zone hybrid space vector pulse-width proposed where optimal selected every carrier cycle. Simulations experimental results validate optimizations.